Data transferred between two devices, for example memory and a processor, or vice versa, over transmission channels (e.g., wires or transmission lines) severely degrades the received data eye (the data eye being a diagram to represent a high speed digital signal). In particular, the transmission channels may introduce moderate to severe Inter Symbol Interference (ISI) for multi-gigabit ranges.
Double data rate (DDR) memory devices transfer data on both the rising and falling edges of a clock signal. Such memory devices require strict control of the timing for the transmission and reception of electrical data and clock/strobe signals. A physical interface (PHY) is coupled between the memory controller and the memory devices, and typically includes circuitry for handling the timing requirements of the data, command, address and associated strobes. For example, the PHY may include delay circuitry configured to properly locate the clock/data strobe in the data eye.
A serial input/output (I/O) link transmits data sequentially over a physical channel. Differential design is often used in a serial I/O link for higher data rates, better performance, and/or longer reach. A serial I/O link PHY typically includes circuitry to handle the timing requirement of the data, at the both a transmitter and a receiver.
What is needed is a solution on either the receiving or transmitting end of a channel to gain additional data eye margins.